In recent years, the electronics industry has looked increasingly to so-called "stacking" of chip carriers and the like to meet information density requirements. Such practice, wherein plural packages overlie common printed circuit board (PCB) real estate, provides a doubling or more of information density, for example, memory capability.
Known efforts in this area have looked to the stacking of chip carriers and dual-in-line packages (DIP) and have provided receptacles having contacts insertable in PCB apertures for soldering thereto and extending upwardly from the PCB to frictionally receive and engage contacts of packages inserted into the receptacles.
Where it is desired to employ the stacked packages electrically independently of one another, the art has looked to several measures for separately addressing the packages. Typically, the contacts of the stacked packages are vertically aligned and circuit paths to the PCB may be redundant to the stacked packages for contacts thereof not involved in package selection. Thus, a single receptacle contact may engage vertically successive package contacts. On the other hand, a unique circuit path is required from the PCB to each package contact providing selection or activation of a package. In one known approach, receptacle contacts are provided with break-away portions, whereby one may interrupt continuity from the PCB to an upper package contact or a lower package contact, despite vertical alignment thereof. In another known approach, package selection contacts are led from the receptacle off-board and are thus not available at the PCB as are all other package contacts. In still another approach, packages are customized to provide for vertically unaligned select/address contacts.
While stacking presents little user difficulty where the stacked packages are used electrically dependently in parallel circuit relation to the PCB, user difficulty is seen in the alternative situation wherein vertical address/select differentiation is required. In the first known approach discussed above, bypassing of one of two vertically aligned package contacts presents a problem in later accessing such bypassed contact from the PCB. Thus, one need define another usable circuit path, for example, from the bypassed package contact to an unused package contact and thence to the PCB through a receptacle contact servicing the unused package contact. In the second discussed approach, the off-board disposition of address/select package contacts precludes accessing from the PCB. The last noted approach requires the tailoring of package contact layout to the receptacle contacts and accordingly does not lend itself to standardization permitting commercial package substitution. Finally, all of the known approaches adopt frictional contact interfitting and do not meet zero insertion force applications.
The above and related approaches are more specifically identified in the statement filed herein pursuant to 37CFR 1.97 and 1.98.